DDC's BU-61580 Bus Controller / Remote Terminal / Monitor Terminal (BC/RT/MT) Advanced Communication Engine (ACE) terminals comprise a complete integrated

interface between a host processor and a MIL-STD-1553 A and B or STANAG 3838 bus.

The ACE series is packaged in a 1.9 -square inch, 70-pin, low-profile, cofired MultiChip Module (MCM) ceramic package that is well suited for applications with stringent height requirements.To minimize board space and "glue" logic, the ACE provides ultimate flexibility in interfacing to a host processor and internal/external RAM.The advanced functional architecture of the ACE terminals provides software compatibility to DDC's Advanced Integrated Multiplexer (AIM) series hybrids, while incorporating a multiplicity of architectural enhancements. It allows flexible operation while off-loading the host processor, ensuring data sample consistency, and supports bulk data transfers.The ACE may be operated at either 12 or 16 MHz. Wire bond options allow for programmable RT address (hardwired is standard) and external transmitter inhibit inputs.

DDC's BU-61580 ACE Integrated BC/RT/MT hybrid provide a complete, flexible interface between a microprocessor and a MIL-STD-1553A, B Notice 2, McAir, or STANAG 3838 bus, implementing Bus Controller, Remote Terminal (RT) and Monitor Terminal (MT) modes. Packaged in a single 1.9-square-inch, 70-pin DIP or surface mountable flatpack or J-lead package, the ACE contains dual low-power transceivers and encoder/decoders, complete BC/RT/MT multi-protocol logic, memory management and interrupt logic, 4K x 16 of shared static RAM and a direct, buffered interface to a host processor bus.

The BU-61580 contains internal address latches and bi-directional data buffers to provide a direct interface to a host processor bus. The BU-61580 may be interfaced directly to both 16-bit and 8-bit microprocessors in a buffered shared RAM configuration. In addition, the ACE may connect to a 16-bit processor bus via a Direct Memory Access (DMA) interface. The BU-65170/61580 includes 4K words of buffered RAM. Alternatively, the ACE may be interfaced to as much as 64K words of external RAM in either the shared RAM or DMA configurations.The ACE RT mode is multi-protocol, supporting MIL-STD-1553A, MIL-STD-1553B Notice 2, STANAG 3838 (including EFAbus), and the McAir A3818, A5232, and A5690 protocols.The memory management scheme for RT mode provides an option for separation of broadcast data, in compliance with 1553B Notice 2. Both double buffer and circular buffer options are programmable by subaddress. These features serve to ensure data consistency and to off-load the host processor for bulk data transfer applications. The ACE series implements three monitor modes: a word monitor, a selective message monitor, and a combined RT/selective monitor. Other features include options for automatic retries and programmable intermessage gap for BC mode, an internal Time Tag Register, an Interrupt Status Register and internal command illegalization for RT mode.

The transceivers in the BU-61580X3(X6) are fully mono-lithic, requiring only a +5 volt power input. Besides eliminating the need for an additional power supply, the use of a 5 volt (only) transceiver requires the use of step-up, rather than step-down, isolation transformers. This provides the advantage of a higher terminal input impedance than is possible for a 15 volt or 12 volt transmitter. As a result, there is greater margin for the input impedance test, mandated for 1553 validation testing. This allows for longer cable lengths between an LRU's system connector and the isolation transformers of an embedded 1553 terminal.

For the +5 V and -15 V/-12 V front end, the BU- 61580X1(X2) uses low-power bipolar analog monolithic and thick-film hybrid technology. The transceiver requires +5 V and -15 V (-12 V) only (requiring no +15 V/+12 V) and includes voltage source transmitters. The voltage source transmitters provide superior line driving capability for long cables and heavy amounts of bus loading. In addition, the monolithic transceivers in the BU-61580X1 provide a minimum stub voltage level of 20 volts peak-to-peak transformer coupled, making them suitable for MIL-STD-1760 applications. The receiver sections of the BU-65170/61580 are fully compliant with MIL-STD-1553B in terms of front end overvoltage protection, threshold, common mode rejection, and word error rate. In addition, the receiver filters have been designed for optimal operation with the J´ chip's Manchester II decoders.

The default mode of operation for the BU-61580 BC/RT/MT requires a 16 MHz clock input. If needed, a software programmable option allows the device to be operated from a 12 MHz clock input. Most current 1553 decoders sample using a 10 MHz or 12 MHz clock. In the 16 MHz mode (default following a hardware or software reset), the ACE decoders sample 1553 serial data using the 16 MHz clock. In the 12 MHz mode, the decoders sample using both clock edges; this provides a sampling rate of 24 MHz. The faster sampling rate for the chip's Manchester II decoders provides superior performance in terms of bit error rate and zero-crossing distortion tolerance.

The ACE includes an internal read/writable Time Tag Register. This register is a CPU read/writable 16-bit counter with a programmable resolution of either 2, 4, 8, 16, 32, or 64 ms per LSB. Also, the Time Tag Register may be clocked from an external oscillator. Another option allows software-controlled incrementing of the Time Tag Register. This supports self-testing for the Time Tag Register. For each message processed, the value of the Time Tag register is loaded into the second location of the respective descriptor stack entry ("TIME TAG WORD") for both BC and RT modes. Additional provided options will: clear the Time Tag Register following a Synchronize (without data) mode command or load the Time Tag Register following a Synchronize (with data) mode command; enable an interrupt request and a bit setting in the Interrupt Status Register when the Time Tag Register rolls over from 0000 to FFFF. Assuming the Time Tag Register is not loaded or reset, this will occur at approximately 4-second time intervals, for 64 ms/LSB resolution, down to 131 ms intervals, for 2 ms/LSB resolution. Another programmable option for RT mode is the automatic clearing of the Service Request Status Word bit following the ACE's response to a Transmit Vector Word mode command.

The ACE series components provide many programmable options for interrupt generation and handling. The interrupt output pin (INT) has three software programmable modes of opera-tion: a pulse, a level output cleared under software control, or a level output automatically cleared following a read of the Interrupt Status Register. Individual interrupts are enabled by the Interrupt Mask Register. The host processor may easily determine the cause of the interrupt by using the Interrupt Status Register. The Interrupt Status Register provides the current state of the interrupt conditions. The Interrupt Status Register may be updated in two ways. In the standard interrupt handling mode, a particular bit in the Interrupt Status Register will be updated only if the condition exists and the corresponding bit in the Interrupt Mask Register is enabled. In the enhanced interrupt handling mode, a particular bit in the Interrupt Status Register will be updated if the condition exists regardless of the contents of the corresponding Interrupt Mask Register bit. In any case, the respective Interrupt Mask Register

bit enables an interrupt for a particular condition.

The software interface of the BU-61580 to the host processor consists of 17 internal operational registers for normal operation, an additional 8 test registers, plus 64K x 16 of shared memory address space. The BU-61580's 4K x 16 of internal RAM resides in this address space. Reference TABLE 1.Definition of the address mapping and accessibility for the ACE's 17 non-test registers, and the test registers, is as follows:

Interrupt Mask Register is used to enable and disable interrupt requests for various conditions.

Configuration Registers #1 and #2 are used to select the BU-61580's mode of operation, and for software control of RT Status Word bits, Active Memory Area, BC Stop-on-Error, RT Memory

Management mode selection, and control of the Time Tag oper-ation.

Start/Reset Register is used for "command" type functions, such as software reset, BC/MT Start, Interrupt Reset, Time Tag Reset, and Time Tag Register Test. The Start/Reset Register includes provisions for stopping the BC in its auto-repeat mode, either at the end of the current message or at the end of the cur-rent BC frame.

BC/RT Command Stack Pointer Register allows the host CPU to determine the pointer location for the current or most recent message when the BU-61580 is in BC or RT modes.

BC Control Word/RT Subaddress Control Word Register. In BC mode, it allows host access to the current, or most recent BC Control Word. The BC Control Word contains bits that select the active bus and message format, enable off-line self-test, masking of Status Word bits, enable retries and interrupts, and specify MIL-STD-1553A or -1553B error handling. In RT mode, this register allows host access to the current or most recent Subaddress Control Word. The Subaddress Control Word is used to select the memory management scheme and enable interrupts for the current message. The read/write accessibility can be used as an aid for testing the ACE.

Time Tag Register maintains the value of a real-time clock. The resolution of this register is programmable from among 2, 4, 8, 16, 32, and 64 ms/LSB. The TAG_CLK input signal also may cause an external oscillator to clock the Time Tag Register. Start-of-Message (SOM) and End-of-Message

(EOM) sequences in BC, RT, and Message Monitor modes cause a write of the current value of the Time Tag Register to the stack area of RAM.

Interrupt Status Register mirrors the Interrupt Mask Register and contains a Master Interrupt bit. It allows the host processor to determine the cause of an interrupt request by means of a single READ operation.

Configuration Registers #3, #4, and #5 are used to enable many of the BU-61580's advanced features. For all three modes, use of the Enhanced Mode enables the various read-only bits in Configuration Register #1. For BC mode, the enhanced mode features include the expanded BC Control Word and BC Block Status Word, additional Stop-On-Error and Stop-On-Status Set functions, frame auto-repeat, programmable intermessage gap times, automatic retries, expanded Status Word Masking, and the

capability to generate interrupts following the completion of any selected message. For RT mode, the enhanced mode features include the expanded RT Block Status Word, the combined RT/Selective Message Monitor mode, internal wrapping of the RTFAIL output signal (from the J´ chip) to the RTFLAG RT Status Word bit, the double buffering scheme for individual receive (broadcast) subaddresses, and the alternate (fully software programmable) RT Status Word. For MT mode, use of the enhanced mode enables use of the Selective Message Monitor, the combined RT/Selective Monitor modes, and the monitor triggering capability.

Data Stack Address Register is used to point to the current address location in shared RAM used for storing message words (second Command Words, Data Words, RT Status Words) in the Selective Word

Monitor mode.

Frame Time Remaining Register provides a read only indication of the time remaining in the current BC frame. The resolution of this register is 100 µs/LSB.

Message Time Remaining Register provides a read only indication of the time remaining before the start of the next message in a BC frame. The resolution of this register is 1 ms/LSB.

BC Frame/RT Last Command/MT Trigger Word Register: In BC mode, it programs the BC frame time, for use in the frame auto-repeat mode. The resolution of this register is 100 ms/LSB, with a range of 6.55 seconds; in RT mode, this register stores the current (or most previous) 1553 Command Word processed by the ACE RT; in the Word Monitor mode, this register specifies a 16-bit Trigger (Command) Word. The

Trigger Word may be used to start or stop the monitor, or to generate interrupts.

Status Word Register and BIT Word Registers provide read-only indications of the BU-65170/61580's RT Status and BIT Words.

Test Mode Registers 0-7: These registers may be used to facilitate production or maintenance testing of the BU-61580 and systems incorporating the BU-61580.

 

 

 

 

 

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The BC protocol of the BU-61580 implements all MIL-STD-1553B message formats. Message format is programmable on a message-by-message basis by means of bits in the BC Control Word and the T/R bit of the Command Word for the respective message. The BC Control Word allows 1553 message format,1553A/B type RT, bus channel, self-test, and Status Word masking to be specified on an individual message basis. In addition, automatic retries and/or interrupt requests may be enabled or disabled for individual messages. The BC performs all error checking required by MIL-STD-1553B. This includes validation of response time, sync type and sync encoding, Manchester II encoding, parity, bit count, word count, Status Word RT Address field, and various RT-to-RT transfer errors. The BU-61580's BC response timeout value is programmable with choices of 18, 22, 50, and 130 µs. The longer response timeout values enable operation over long buses and/or the use of repeaters. FIGURE 2 illustrates BC intermessage gap and frame timing. The BU-61580 may be programmed to process BC frames of up to 512 messages with no processor intervention. It is possible to program for either single frame or frame auto-repeat operation. In the auto-repeat mode, the frame repetition rate may be controlled either internally, using a programmable BC frame timer, or from an external trigger input. The internal BC frame time is programmable up to 6.55 seconds in increments of 100 µs. In addition to BC frame time, intermessage gap time, measured from the start of the current message to the start of the subsequent message, is programmable on an individual message basis. The time between individual successive messages is programmable up to 65.5 ms, in increments of 1 µs.

TABLE 25 illustrates a typical memory map for BC mode. It is important to note that the only fixed locations for the BU-61580 in the Standard BC mode are for the two Stack Pointers (address locations 0100 (hex) and 0104) and for the two Message Count locations (0101 and 0105). Enabling the Frame Auto-Repeat mode will reserve four more memory locations for use in the Enhanced BC mode; these locations are for the two Initial Stack Pointers (address locations 102 (hex) and 106) and for the Initial Message Count locations (103 and 107). The user is free to locate the Stack and BC Message Blocks anywhere else within the 64K (4K internal) shared RAM address space. For simplicity of llustration, assume the allocation of the maximum length of a BC message for each message block in the typical BC memory map of TABLE 25. The maximum size of a BC message block is 38 words, for an RT- to-RT transfer of 32 Data Words (Control + 2 Commands + Loopback + 2 Status Words + 32 Data Words).

Note, however, that this example assumes the disabling of the 256-word boundaries.

FIGURE 3 illustrates the BU-61580's BC memory management scheme. One of the BC memory management features is the global double buffering mechanism. This provides for two sets of the various BC mode data structures: Stack Pointer and Message Counter locations, Descriptor Stack areas, and BC message blocks. Bit 13 of Configuration Register #1 selects the current active area. At any point in time, the BU-61580's internal 1553 memory management logic may access only the various data structures within the "active" area. FIGURE 3 delineates the "active" and "inactive" areas by the nonshaded and shaded areas, respectively; however, at any point in time, both the "active" and "nonactive" areas are accessible by the host processor. In most applications, the host processor will access the "nonactive" area, while the 1553 bus processes the "active" area messages. The BC may be programmed to transmit multimessage frames of up to 512 messages. The number of messages to be processed is programmable by the Active Area Message Count location in the shared RAM, initialized by the host processor. In addition, the host processor must initialize another location, the Active Area Stack Pointer. The Stack Pointer references the four-word message block descriptor in the Stack area of shared RAM for each message to be processed. The BC Stack size is programmable with choices of 256, 512, 1024, and 2048 words. In the BC Frame Auto-Repeat mode, the Initial Stack Pointer and Initial Message Counter locations must be loaded by the host prior to the processing of the first frame. The single frame mode does not use these two locations. The third and fourth words of the BC block descriptor are the Intermessage Gap Time and the Message Block Address for the respective message. These two memory locations must be written by the host processor prior to the start of message processing. Use of the Intermessage Gap Time is optional. The Block Address pointer specifies the starting location for each message block. The first word of each BC message block is the BC Control Word.

At the start and end of each message, the Block Status and Time Tag Words write to the message block descriptor in the stack. The Block Status Word includes indications of message in process or message completion, bus channel, status set, response timeout, retry count, status address mismatch, loop test (on-line self-test) failure, and other error conditions. TABLE 21 illustrates the bit mapping of the BC Block Status word. The 16-bit Time Tag Word will reflect the current contents of the internal Time Tag Register. This read/writable register, which oper-ates for all three modes, has programmable resolution of from 2 to 64 µs/LSB. In addition, the Time Tag register may be clocked from an external source.

In BC mode, the BU-61580 supports all MIL-STD-1553 message formats. For each 1553 message format, the BU-61580 man-dates a specific sequence of words within the BC Message Block. This includes locations for the Control, Command and (transmitted) Data Words that are to be read from RAM by the BC protocol logic. In addition, subsequent contiguous locations must be allocated for storage of received Loopback, RT Status and Data Words. FIGURE 4 illustrates the organization of the BC message blocks for the various MIL-STD-1553 message formats. Note that for all of the message formats, the BC Control Word is located in the first location of the message block. For each of the BC Message Block formats, the first word in the block is the BC Control Word. The BC Control Word is not transmitted on the 1553 bus. Instead, it contains bits that select the active bus and message format; enable off-line self-test; masking of Status Word bits; enable retries and interrupts; and specifies MIL-STD-1553A or -1553B error handling. The bit mapping and definitions of the BC Control Word are illustrated in TABLE 8.

The BC Control Word is followed by the Command Word to be transmitted, and subsequently by a second Command Word (for an RT-to-RT transfer), followed by Data Words to be transmitted (for Receive commands). The location after the last word to be transmitted is reserved for the Loopback Word. The Loopback Word is an on-line self-test feature. The subsequent locations after the Loopback Word are reserved for received Status Words and Data Words (for Transmit commands).

The BU-61580 BC implements automatic message retries. When enabled, retries will occur, following response timeout or format error conditions. As additional options, retries may be enabled when the Message Error Status Word bit is set by a 1553A RT or following a "Status Set" condition. For a failed message, either one or two message retries will occur, the bus channel (same or alternate) is independently programmable for the first and second retry attempts. Retries may be enabled or disabled on an individual message basis.

BC interrupts may be enabled by the Interrupt Mask Register for Stack Rollover, Retry, End-of-Message (global), End-of-Message (in conjunction with the BC Control Word for individual messages), response timeout, message error, end of BC frame, and Status Set conditions. The definition of "Status Set" is pro-grammable on an individual message basis, by means of the BC Control Word. This allows for masking ("care/don't care") of the individual RT Status Word bits.

One of the salient features of the ACE's RT architecture is its true multiprotocol functionality. This includes programmable options for support of MIL-STD-1553A, the various McAir protocols, and MIL-STD-1553B Notice 2. The BU-61580 RT response time is 2 to 5 µs dead time (4 to 7 µs per 1553B), providing compliance to all the 1553 protocols. Additional multiprotocol features of the BU-61580 include options for full software control of RT Status and Built-in-Test (BIT) words. Alternatively, for 1553B applications, these words may be formulated in real time by the BU-61580 protocol logic. The BU-61580 RT protocol design implements all the MIL-STD-1553B message formats and dual redundant mode codes. This design is based largely on previous generation products that have passed SEAFAC testing for MIL-STD-1553B com-pliance. The ACE RT performs comprehensive error checking, word and format validation, and checks for various RT-to-RT transfer errors. Other key features of the BU-61580 RT include a set of interrupt conditions, internal command illegaliza-tion, and programmable busy by subaddress.

TABLE 26 illustrates a typical memory map for the BU-61580 in RT mode. As in BC mode, the two Stack Pointers reside in fixed locations in the shared RAM address space: address 0100 (hex) for the Area A Stack Pointer and address 0104 for the Area B Stack Pointer. Besides the Stack Pointer, for RT mode there are several other areas of the ACE address space designated as fixed locations. All RT modes of operation require the Area A and Area B Lookup Tables. Also allocated are several fixed locations for optional features: Command Illegalization Lookup Table, Mode Code Selective Interrupt Table, Mode Code Data Table, and Busy Bit Lookup Table. It should be noted that any unen-abled optional fixed locations may be used for general purpose storage (data blocks). The RT Lookup tables, which provide a mechanism for mapping data blocks for individual Tx/Rx/Bcst-subaddresses to areas in the RAM, occupy address range locations are 0140 to 01BF for Area A and 01C0 to 023F for Area B. The RT lookup tables include Subaddress Control Words and the individual Data Block Pointers. If used, address range 0300-03FF will be dedicated as the illegalizing section of RAM. The actual Stack RAM area and the individual data blocks may be located in any of the nonfixed areas in the shared RAM address space.

One of the salient features of the ACE series products is the flexibility of its RT memory management architecture. The RT architecture allows the memory management scheme for each trans-mit, receive, or broadcast subaddress to be programmable on a subaddress basis. Also, in compliance with MIL-STD-1553B Notice 2, the BU-65170/61580 provides an option to separate data received from broadcast messages from nonbroadcast received data. Besides supporting a global double buffering scheme (as in BC mode), the ACE RT provides a pair of 128-word Lookup Tables for memory management control. They are programmable on a subaddress basis (refer to TABLE 27). These 128-word tables include 32-word tables for transmit message pointers and receive message pointers. There is also a third, optional Lookup Table for broadcast message pointers, providing Notice 2 compliance, if necessary. The fourth section of each of the RT Lookup Tables stores the 32 Subaddress Control Words (refer to TABLE 9 and 28). The individual Subaddress Control Words may be used to select the RT memory management option and interrupt scheme for each transmit, receive, and (optionally) broadcast subaddress. For each transmit subaddress, there are two possible memory management schemes: (1) single message; and (2) circular buffer. For each receive (and optionally broadcast) subaddress, there are three possible memory management schemes: (1) single message; (2) double buffered; and (3) circular buffer. For each transmit, receive and broadcast subaddress, there are two interrupt conditions that are programmable by the respective Subaddress Control Word: (1) after every message to the subaddress; (2) after a circular buffer rollover. An additional table in RAM may be used to enable interrupts following selected mode code messages. When using the circular buffer scheme for a given subaddress, the size of the circular buffer is programmable by three bits of the Subaddress Control Word (see TABLE 28). The options for cir-cular buffer size are 128, 256, 512, 1024, 2048, 4096, and 8192 Data Words.

FIGURE 5 illustrates the RT Single Message memory manage-ment scheme. When operating the BU-61580 in its "AIM-HY" (default) mode, the Single Message scheme is implemented for all transmit, receive, and broadcast subaddresses. In the Single Message mode (also in the Double Buffer and Circular Buffer modes), there is a global double buffering scheme, controlled by bit 13 of Configuration Register #1. This selects from between the two sets of the various data structures shown in the figure: the Stack Pointers (fixed addresses), Descriptor Stacks (user defined addresses), RT Lookup Tables (fixed addresses), and RT Data Word blocks (user defined addresses). FIGURES 27, 28, and 29 delineate the "active" and "nonactive" areas by the nonshaded and shaded areas, respectively. As shown, the ACE stores the Command Word from each message received, in the fourth location within the message descriptor (in the stack) for the respective message. The T/R bit, subaddress field, and (optionally) broadcast/own address, index into the active area Lookup Table, to locate the data block pointer for the current message. The BU-65170/61580 RT memory management logic then accesses the data block pointer to locate the starting address for the Data Word block for the current message. The maximum size for an RT Data Word block is 32 words. For a particular subaddress in the Single Message mode, there is overwriting of the contents of the data blocks for receive/broadcast subaddresses or overreading, for transmit subaddresses. In the single message mode, it is possible to access multiple data blocks for the same subaddress. This, however, requires the intervention of the host processor to update the respective Lookup Table pointer. To implement a data wraparound subaddress, as required by Notice 2 of MIL-STD-1553B, the Single Message scheme should be used for the wraparound subaddress. Notice 2 recommends subaddress 30 as the wraparound subaddress.

FIGURE 6 illustrates the RT circular buffer memory management scheme. The circular buffer mode facilitates bulk data transfers. The size of the RT circular buffer, shown on the right side of the figure, is programmable from 128 to 8192 words (in even powers of 2) by the respective Subaddress Control Word. As in the single message mode, the host processor initially loads the individual Lookup Table entries. At the start of each message, the ACE stores the Lookup Table entry in the third position of the respective

message block descriptor in the stack area of RAM, as in the Single Message mode. The ACE transfers Receive or Transmit Data Words to (from) the circular buffer, starting at the location referenced by the Lookup Table pointer. At the end of a valid (or optionally invalid) message, the value of the Lookup Table entry updates to the next location after the last address accessed for the current message. As a result, Data Words for the next message directed to the same Tx/RX(/Bcst) subaddress will be accessed from the next contiguous block of address locations within the circular buffer. As a recommended option, the Lookup Table pointers may be programmed to not update following an invalid receive (or broadcast) message. This allows the 1553 bus controller to retry the failed message, resulting in the valid (retried) data overwriting the invalid data. This eliminates overhead for the RT's host processor. When the pointer reaches the lower boundary of the circular buffer (located at 128, 256, . . . 8192-word boundaries in the BU-61580 address space), the pointer moves to the top boundary of the circular buffer, as FIGURE 6 shows.

The use of the Circular Buffer scheme is ideal for bulk data transfers; that is, multiple messages to/from the same subaddress. The recommendation for such applications is to enable the circular buffer interrupt request. By so doing, the routine transfer of multiple messages to the selected subaddress, including errors and retries, is transparent to the RT's host processor. By strategically initializing the subaddresses' Lookup Table pointer prior to the start of the bulk transfer, the BU-61580 may be con-figured to issue an interrupt request only after it has received the anticipated number of valid Data Words to the designated sub-address.

For receive (and broadcast) subaddresses, the BU-61580 RT offers a third memory management option, Subaddress Double Buffering. Subaddress Double Buffering provides a means of ensuring data consistency. FIGURE 70 illustrates the RT Subaddress Double Buffering scheme. Like the Single Message and Circular Buffer modes, the Double Buffering mode may be selected on a subaddress basis by means of the Subaddress Control Word. The purpose of the Double Buffering mode is to provide

the host processor a convenient means of accessing the most recent, valid data received to a given subaddress.This serves to ensure the highest possible degree of data consistency by allocating two 32-bit Data Word blocks for each individual receive (and/or broadcast) subaddress.

At a given point in time, one of the two blocks will be designated as the "active" 1553 data block while the other will be designated as the "inactive" block. The Data Words from the next receive message to that subaddress will be stored in the "active" block. Upon completion of the message, provided that the message was valid and Subaddress Double Buffering is enabled, the BU- 61580 will automatically switch the "active" and "inactive" blocks for the respective subaddress. The ACE accomplishes this by toggling bit 5 of the subaddress's Lookup Table Pointer and rewriting the pointer. As a result, the most recent valid block of received Data Words will always be readily accessible to the host processor.

As a means of ensuring data consistency, the host processor is able to reliably access the most recent valid, received Data Word block by performing the following sequence:

(1) Disable the double buffering for the respective subaddress by the Subaddress Control Word. That is, temporarily switch the subaddress' memory management scheme to the Single Message mode.

(2) Read the current value of the receive (or broadcast) sub-address's Lookup Table pointer. This points to the current "active" Data Word block. By inverting bit 5 of this pointer value, it is possible to locate the start of the "inactive" Data Word block. This block will contain the Data Words received during the most recent valid message to the subaddress.

(3) Read out the words from the "inactive" (most recent) Data Word Block.

(4) Re-enable the Double Buffering mode for the respective subaddress by the Subaddress Control Word.

As in BC mode, the BU-61580 RT provides many maskable interrupts. RT interrupt conditions include End of (every) Message, Message Error, Selected Subaddress (Subaddress Control Word) Interrupt, Circular Buffer Rollover, Selected Mode Code Interrupt, and Stack Rollover.

At the beginning and end of each message, the BU-61580 RT stores a four-word message descriptor in the active area stack. The RT stack size is programmable, with choices of 256, 512, 1024, and 2048 words. FIGURES 5, 6 and 7 show the four words: Block Status Word, Time Tag Word, Data Block Pointer, and the 1553 received Command Word. The RT Block Status Word includes indications of message in-progress or message complete, bus channel, RT-to-RT transfer and RT-to-RT transfer errors, message format error, loop test (self-test) failure, circular buffer rollover, illegal command, and other error con-ditions. TABLE 22 shows the bit mapping of the RT Block Status Word.

As in BC mode, the Time Tag Word stores the current contents of the BU-65170/61580's read/writable Time Tag Register. The resolution of the Time Tag Register is programmable from among 2, 4, 8, 16, 32, and 64 µs/LSB. Also, incrementing of the Time Tag counter may be from an external clock source or via software command.

The ACE stores the contents of the accessed Lookup Table location for the current message, indicating the starting location of the Data Word block, as the Data Block Pointer. This serves as a convenience in locating stored message data blocks. The ACE stores the full 16-bit 1553 Command Word in the fourth location

of the RT message descriptor.

The BU-65170/61580 provides an internal mechanism for RT command illegalization. In addition, the Busy Status Word bit can be set so that it is only a programmed subset of the transmit/ receive/broadcast subaddresses. The illegalization scheme uses a 256-word area in the BU-61580's address space. A benefit of this feature is the reduction of printed circuit board requirements, by eliminating the need for an external PROM, PLD, or RAM device that does the illegalizing function. The BU-J1165170/61580's illegalization scheme provides maximum flexibility, allowing any subset of the 4096 possible combinations of broadcast/own address, T/R bit, subaddress, and wordcount/mode code to be illegalized. Another advantage of the RAM-based illegalization technique is that it provides for a high degree of self-testability.

TABLE 29 illustrates the addressing scheme of the illegalization RAM . As shown, the base address of the illegalizing RAM is 0300 (hex). The ACE formulates the index into the Illegalizing Table based on the values of BROADCAST/OWN ADDRESS, T/R bit, Subaddress, and the MSB of the Word Count/Mode

Code field (WC/MC4) of the current Command Word. The internal RAM has 256 words reserved for command illegal-ization. Broadcast commands may be illegalized separately from nonbroadcast receive commands and mode commands. Commands may be illegalized down to the word count level. For

example, a one-word receive command to subaddress 1 may be legal, while a two-word receive command to subaddress 1 may be illegalized. The first 64 words of the Illegalization Table refer to broadcast

receive commands (two words per subaddress). The next 64 words refer to broadcast transmit commands. Since nonmode code broadcast transmit commands are by definition invalid, this section of the table (except for subaddresses 0 and 31) does not need to be initialized by the user. The next 64 words correspond to nonbroadcast receive commands. The final 64 words refer to nonbroadcast transmit commands. Messages with Word Count/Mode Code (WC/MC) fields between 0 and 15 may be illegalized

by setting the corresponding data bits for the respective even-numbered address locations in the illegalization table. Likewise,messages with WC/MC fields between 16 and 31 may be illegalized by setting the corresponding data bits for the respective odd-numbered address locations in the illegalization table.

The following should be noted with regards to command illegal-ization:

(1) To illegalize a particular word count for a given broad-cast/own address-T/R subaddress, the appropriate bit position in the respective illegalization word should be set to logic 1. A bit value of logic 0 designates the respective Command Word as a legal command. The ACE will respond to an illegalized nonbroadcast command with the Message Error bit set in its RT Status Word.

(2) For subaddresses 00001 through 11110, the "WC/MC" field specifies the Word Count field of the respective Command Word. For subaddresses 00000 and 11111, the "WC/MC" field specifies the Mode Code field of the respective Command Word.

(3) Since nonmode code broadcast transmit messages are not defined by MIL-STD-1553B, the sixty (60) words in theillegalization RAM, addresses 0342 through 037D, corre-sponding to these commands do not need to be initialized. The ACE will not respond to a nonmode code broadcast transmit command, but will automatically set the Message Error bit in its internal Status Register, regardless of whether or not corresponding bit in the illegalization RAM has been set. If the next message is a Transmit Status or Transmit Last Command mode code, the ACE will respond with its Message Error bit set.

As a means of providing compliance with Notice 2 of MIL-STD-1553B, the BU-65170/61580 RT provides a software controllable means for setting the Busy Status Word bit as a function of sub-address. By a Busy Lookup Table in the BU-65170/61580 address space, it is possible to set the Busy bit based on command broadcast/own address, T/R bit, and subaddress. Another programmable option, allows received Data Words to be either stored or not stored for messages, when the Busy bit is set.

The BU-65170/61580 allows the hardwired RT Address to be read by the host processor. Also, there are options for the RT FLAG Status Word bit to be set under software control and/or automatically following a failure of the loopback self-test. Other software controllable RT options include software programmable RT Status and RT BIT words, automatic clearing of the Service Request Status Word bit following a Transmit Vector Word mode command, capabilities to clear and/or load the Time Tag Register following receipt of Synchronize mode commands, options regarding Data Word transfers for the Busy and/or Message Error (Illegal) Status Word bits, and for handling of 1553A and reserved mode codes.

The BU-61580 provides three bus monitor (MT) modes:

(1) The "AIM-HY" (default) or "AIM-HY'er" Word Monitor mode.

(2) A Selective Message Monitor mode.

(3) A Simultaneous Remote Terminal/Selective Message Monitor mode.

The strong recommendation for new applications is the use of the Selective Message Monitor, rather than the Word Monitor. Besides providing monitor filtering based on RT Address, T/R bit, and Subaddress, the Message Monitor eliminates the need to determine the start and end of messages by software. The devel-opment of such software tends to be a tedious task. Moreover, at run time, it tends to entail a high degree of CPU overhead.

In the Word Monitor mode, the BU-61580 monitors both 1553 buses. After initializing the Word Monitor and putting it on-line the BU-61580 stores all Command, Status, and Data Words received from both buses. For each word received from either bus, the BU-61580 stores a pair of words in RAM. The first word is the 16 bits of data from the received word. The second word is the Monitor Identification (ID), or "Tag" word. The ID Word contains information relating to bus channel, sync type, word validity, and interword time gaps. The BU-61580 stores data and ID words in a circular buffer in the shared RAM address space. TABLE 23 shows the bit mapping for the Monitor ID word.

There is a Trigger Word Register that provides additional flexibility for the Word Monitor mode. The BU-61580 stores the value of the 16-bit Trigger Word in the MT Trigger Word Register. The contents of this register represent the value of the Trigger Command Word. The BU-61580 has programmable options to start or stop the Word Monitor, and/or to issue an interrupt request following receipt of the Trigger Command Word from the 1553 bus.

The BU-61580 Selective Message Monitor provides features to greatly reduce the software and processing burden of the host CPU. The Selective Message Monitor implements selective monitoring of messages from a dual 1553 bus, with the monitor filtering based on the RT Address, T/R bit, and Subaddress fields of received 1553 Command Words. The Selective Message Monitor mode greatly simplifies the host processor software by distinguishing between Command and Status Words. The Selective Message Monitor maintains two stacks in the BU-61580 RAM: a Command Stack and a Data Stack.

The Selective Message Monitor may function as a purely passive monitor or may be programmed to function as a simultaneous RT/Monitor. The RT/Monitor mode provides complete Remote Terminal (RT) operation for the BU-61580's strapped RT address and bus monitor capability for the other 30 nonbroadcast RT addresses. This allows the BU-61580 to simultaneously operate as a full function RT and "snoop" on all or a subset of the bus activity involving the other RTs on a bus. This type of operation is sometimes needed to implement a backup bus controller. The combined RT/Selective Monitor maintains three stack areas in the BU-61580 address space: an RT Command Stack, a Monitor Command Stack, and a Monitor Data Stack. The pointers for the various stacks have fixed locations in the BU-61580 address space.

TABLE 30 illustrates a typical memory map for the ACE in the Selective Message Monitor mode. This mode of operation defines several fixed locations in the RAM. These locations allocate in a manner that is compatible with the combined RT/Selective Message Monitor mode. Refer to TABLE 7 for an example of a typical Selective Message Monitor Memory Map. The fixed memory map consists of two Monitor Command Stack Pointers (location 102h and 106h), two Monitor Data Stack Pointers (locations 103h and 107h), and a Selective Message Monitor Lookup Table (0280-02FFh) based on RT Address, T/R, and subaddress. Assume a Monitor Command Stack size of 1K words, and a Monitor Data Stack size of 2K words.

Refer to FIGURE 8 for an illustration of the Selective Message Monitor operation. Upon receipt of a valid Command Word, the BU-61580 will reference the Selective Monitor Lookup Table (a fixed block of addresses) to check for the condition (disabled/enabled) of the current command. If disabled, the BU-61580 will ignore (and not store) the current message; if enabled, the BU-61580 will create an entry in the Monitor Command Stack at the address location referenced by the Monitor Command Stack Pointer.

Similar to RT mode, The ACE stores a Block Status Word, 16-bit Time Tag Word, and Data Block Pointer in the Message Descriptor, along with the received 1553 Command Word following reception of the Command Word. The ACE writes the Block Status and Time Tag Words at both the start and end of the message. The Monitor Block Status Word contains indications of message in-progress or message complete, bus channel, Monitor Data Stack Rollover, RT-to-RT transfer and RT-to-RT transfer errors, message format error, and other error conditions. TABLE 24 shows the Message Monitor Block Status Word. The Data Block Pointer references the first word stored in the Monitor Data Stack (the first word following the Command Word) for the current message. The BU-61580 will then proceed to store the subsequent words from the message (possible second Command Word, Data Word(s), Status Word(s)) into consecutive locations in the Monitor Data Stack.

The size of the Monitor Command Stack is programmable to 256, 1K, 4K, or 16K words. The Monitor Data Stack size is programmable to 512, 1K, 2K, 4K, 8K, 16K, 32K, or 64K words.

Monitor interrupts may be enabled for Monitor Command Stack Rollover, Monitor Data Stack Rollover, and/or End-of-Message conditions. In addition, in the Word Monitor mode there may be an interrupt enabled for a Monitor Trigger condition.